Using a Performance Model to Implement a Superscalar CVA6

Open-Source RISC-V: Energy Efficiency of Superscalar, Out-of-Order Execution

Fixing a Performance Regression in LLVM's SLP Vectorizer on RISC-V

The article describes how the author solved a performance regression in LLVM's SLP Vectorizer by analyzing a benchmark from a RISC-V target.

Technical Analysis of Ultrassembler's High-Speed RISC-V Assembly Performance

Ultrassembler is a high-performance RISC-V assembler library developed as part of the Chata signal processing project. The article explains

Personal Experience with ARM and RISC-V Architectures: Benefits and Challenges

The author shares their personal experience with ARM and RISC-V architectures, expressing both appreciation for ARM's low-cost, energy-effic

iRISC: A New Processor Architecture Combining RISC-V Open Source with Performance-Focused Design

The article discusses iRISC, a new processor architecture that combines RISC-V's open-source approach with Apple's performance-focused desig

Using llvm-mca to Analyze and Optimize C++ Code Performance

This article from the Abseil Performance Tip of the Week series demonstrates how to use llvm-mca (Machine Code Analyzer) to analyze and opti