Reverse-Engineered Analysis of Apple Neural Engine Architecture Across A11-A18 and M1-M5 Chips
This article presents a reverse-engineered technical analysis of the Apple Neural Engine (ANE), the fixed-function matrix accelerator found in Apple's A-series and M-series chips. Based on direct measurement and static analysis of private runtime, compiler, kernel driver, and firmware, it documents the ANE's datapath, roofline performance bounds, dispatch route below Core ML, compiler and program format, weight-compression scheme, and the kernel driver/firmware/command protocol. Coverage spans A11 through A18 and M1 through M5 families, with claims labeled by evidence type (measured, decompile-derived, or predicted). It notes that while a direct user-space route exists for research and measurement, Core ML remains the only supported path for shipping software.
Key quotes
The Apple Neural Engine (ANE) is the fixed-function matrix accelerator that has shipped in Apple systems-on-chip since the A11-class iPhone and iPad chips and the M1-class Mac chips, exposed to applications only through the Core ML model framework.
This guide reports a reverse-engineered account of the engine, based on direct measurement on Apple silicon and static analysis of the private runtime, compiler, kernel driver, and firmware.
Claims are labeled as measured, decompile-derived, or predicted, and the methodology and open questions are recorded.
The direct route is callable from ordinary user space but remains undocumented, unsupported, and version-fragile; it is intended for measurement, research, and on-device work, not for shipping software, where Core ML remains the supported path.
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