Designing a Systolic Array AI Accelerator in Two Weeks for Global Foundries 180nm Tapeout
By
client4
Pulled from the oven just right. Trustworthy, fact-dense, deeply satisfying.
Summary
The article details the author's ambitious project to design a systolic array AI accelerator with in-silicon debug infrastructure from scratch in under two weeks, taking advantage of a free experimental shuttle using Global Foundries 180nm technology through Tiny Tapeout. The author shares their journey of creating a JTAG interface and developing a free and open-source silicon-proven AI accelerator, framing it as a potentially 'bad idea' due to the tight timeline and complexity of the task. The content chronicles the technical challenges, design decisions, and the process leading up to the tapeout deadline.
Key quotes
· 4 pulledSo when the opportunity arose to join an experimental shuttle using global foundries 180nm for FREE I jumped onto the opportunity and designed my own JTAG!
Chronicles of a bad idea. Or how I designed a systolic array with in-silicon debug infrastructure from scratch in under two weeks, and taped it out on Global Foundry 180 nm though a Tiny Tapeout experimental shuttle.
Frankly, I would love to tell you a great story about how I went into this wanting to design a free and open source silicon proven AI accelerator that the community
Living under rocks#As anyone that hasn't been living under a rock might have heard, AI accelerators are the coolest kids in town these days.
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