Shift-and-Add (SAdd): Hardware-Aware Channel Characterization With Polar NRZ Stimuli

High-bandwidth wireline transceivers rely on stochastic adaptation algorithms, such as the Least Mean Squares (LMS) method for equalizer calibration. While effective, these methods cannot provide upper-bounded latency guarantees, require tuning step-size parameters, and can be burdened by error propagation when calibrating Decision Feedback Equalizers (DFEs). However, if a high-fidelity estimate of the channel response is known, an alternative approach is to configure an equalizer to directly compensate for channel-induced distortion. To address the challenges of low-latency adaptation in wireline transceivers, we co-design a novel hardware-aware algorithm and a digital architecture for training-based channel response identification. We define and leverage a subset of polar Non Return to Zero (NRZ) stimulus that we refer to as Shift-and-Add (SAdd) sequences, which are designed to simultaneously favor an efficient hardware design and provide low noise amplification with precisely defined estimator variance properties. For deployment in practical resource-constrained wireline transceivers, we present an algorithm and architecture with low latency, upper-bounded computation time, low memory usage, and few arithmetic operations.