IBM pursues sequential transistor stacking for next-generation chip design, diverging from rivals
By
Samuel K. Moore
Summary
IBM has presented research at the IEEE VLSI Symposium detailing a different approach to next-generation transistor design. While all major chipmakers agree that future transistors will involve stacking two transistors vertically (complementary FET or CFET), IBM's path diverges from Intel, Samsung, and TSMC. IBM is pursuing a sequential stacking approach where the bottom transistor is built first, then the top transistor is fabricated on top using lower-temperature processes. This contrasts with the monolithic approach favored by others, where both transistors are built simultaneously. The sequential method offers advantages in design flexibility and thermal budget management but introduces challenges in alignment and defect control. Commercial introduction is expected around 2030.
Source
bskyIBM pursues sequential transistor stacking for next-generation chip design, diverging from rivalsspectrum.ieee.orgKey quotes
· 3 pulledChipmakers agree that the transistor of the next decade will actually be two transistors stacked atop one another, packing in many more devices in the same area of silicon and leading to circuits that are as little as half the size of today's.
But their research efforts are beginning to show some important divergence in the details.
Commercial introduction is likely six years away, so they are far from a final version, but research presented last week at IEEE VLSI Symposium in Honolulu and detailed today by IBM points toward two main paths.
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