TinyTinyTPU: Educational Implementation of Google's TPU Architecture on FPGA
By
Xenograph
Slow-proofed and worth the wait. Worth its weight in flour.
Summary
TinyTinyTPU is an educational implementation of Google's TPU (Tensor Processing Unit) architecture, scaled down to a minimal 2×2 systolic array matrix-multiply unit. The project is implemented in SystemVerilog and deployed on FPGA hardware (specifically Basys3 XC7A35T). It serves as a learning resource demonstrating TPU architecture principles, including complete implementation with simulation/testing, FPGA build/deployment, and inference capabilities. The project includes documentation on resource usage, project structure, architecture details, and open-source tooling using Yosys/nextpnr.
Key quotes
· 4 pulledTinyTinyTPU is an educational implementation of Google's TPU architecture, scaled down to a 2×2 systolic array
A minimal 2×2 systolic-array TPU-style matrix-multiply unit, implemented in SystemVerilog and deployed on FPGA
This project implements a complete TPU architecture including resource usage on Basys3 XC7A35T FPGA
Demonstrates design philosophy as a minimal, educational implementation of TPU architecture
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