Optimizing SBCL Assembly: Fixing Wasteful Machine Code Encoding in the F18 NEXT Sequence
By
yacin
A baker's-dozen of insight crammed into one ring.
Summary
A technical blog post examining SBCL (Steel Bank Common Lisp) as an assembly code breadboard, focusing on low-level optimization of the NEXT sequence used in the F18 Forth processor implementation. The author discusses machine code encoding inefficiencies, specifically how effective addresses with index registers but no base register were being encoded wastefully, and shows how a fix reduced the instruction size from 14 bytes to 9 bytes.
Key quotes
· 3 pulledEDIT: Lutz Euler points out that the NEXT sequence (used to) encode an effective address with an index register but no base.
The mistake doesn't affect the meaning of the instruction, but forces a wasteful encoding.
As usual with Chuck Moore's work, it's hard to tell the difference between insanity and mere brilliance ;)
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