Introducing the SUS Hardware Description Language for High-Performance Hardware Designs
By
nateb2022
Hard crust, hollow middle. Skim only.
Summary
The SUS Hardware Description Language aims to compete with Synthesizeable Verilog and VHDL by providing an intuitive and thin syntax for building netlists without imposing specific design paradigms on hardware designers.
Key quotes
· 2 pulledThe SUS HDL is meant to be a direct competitor to Synthesizeable Verilog and VHDL.
SUS shall impose no paradigm on the hardware designer, such as requiring specific communication protocols or iteration constructs.
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