How CPU Architecture Became Hostage to C Programming's Function Paradigm
By
rajiv_abraham
A baker's-dozen of insight crammed into one ring.
Summary
The article critiques how modern CPU architecture has been shaped by the dominance of the C programming language and the 'everything-is-a-function' paradigm. It argues that hardware features like frame pointer registers and stack management represent a massive silicon investment dedicated to making synchronous function calls efficient, rather than exploring alternative computational models like message-passing or different register architectures. The piece suggests this represents a form of 'hardware Stockholm syndrome' where we've become psychologically attached to a particular abstraction that won historically, rather than it being fundamentally superior.
Key quotes
· 3 pulledIt's a monument to C and to the everything-is-a-function paradigm. Not because this paradigm discovered some fundamental truth about computation. Because it won, and winners get to reshape reality in their image.
Those transistors could have been general-purpose registers. Could have been message-passing hardware. Could have been anything. Instead, they're dedicated to making one particular abstraction - blocking, synchronous function calls - cheaper.
Look at a modern CPU die. See those frame pointer registers? That stack management hardware? That's real estate. Silicon. Transistor budget.
You might also wanna read
Reverse-engineering the Intel 8087: A look at microcode and register exchange
A detailed technical deep-dive into the Intel 8087 floating-point co-processor's microcode, specifically examining the register exchange ope
righto.com·1d ago
Zero-Copy GPU Inference from WebAssembly on Apple Silicon: Direct Memory Sharing Between Wasm and GPU
The article describes a technical breakthrough on Apple Silicon where WebAssembly modules can share linear memory directly with the GPU, ena
abacusnoir.com·1mo ago
Understanding CPU Pipelining and Its Evolution into Branch Prediction
This article explores CPU pipelining concepts as part of a branch prediction series, explaining how modern processors optimize instruction e
Tailslayer: C++ Library for Reducing RAM Tail Latency from DRAM Refresh Stalls
Tailslayer is a C++ library designed to reduce tail latency in RAM reads caused by DRAM refresh stalls. It works by replicating data across
github.com·1mo ago
Understanding CPU Branch Prediction and Its Impact on Benchmarking
The article discusses how modern processors use branch prediction to execute multiple instructions per cycle, explaining that CPUs have rema
lemire.me·2mo ago
nCPU: AI-Native Computing Platform with Neural Network-Based Architecture
nCPU is an AI-native computing platform where every layer from arithmetic to operating system to compiler is either a trained neural network
github.com·2mo ago