Semiconductor Metrology Faces Challenges as Chip Manufacturing Goes Vertical
By
Pat Brans
Hand-rolled, kettle-boiled, baked to perfection. Worth every minute at the bakery.
Summary
The semiconductor industry is facing a metrology crisis as chip manufacturing shifts from planar (2D) to vertical (3D) architectures. Traditional top-down inspection methods like optical metrology and CD-SEM, optimized for lateral scaling, are inadequate for measuring buried structures in gate-all-around transistors, HBM memory, vertically stacked NAND, and future CFET designs. The article explores how metrology tools must evolve to reconstruct and measure complex 3D structures deep within chips, highlighting the growing gap between advanced manufacturing capabilities and inspection technology.
Key quotes
· 3 pulledSemiconductor inspection has traditionally meant looking down.
Optical metrology and critical dimension scanning electron microscopy (CD-SEM) systems were optimized for lateral scaling, where the central challenge was shrinking dimensions across the surface of silicon.
Today, however, advanced-node manufacturing is moving increasingly into the Z-axis.
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