imec's 2T0C IGZO-based DRAM cell could enable high-density 3D DRAM and embedded memory
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Summary
This article from imec explores a novel DRAM memory cell design using two IGZO (indium-gallium-zinc-oxide)-based transistors (2T0C) as an alternative to the traditional 1T1C silicon-based DRAM cell. The 2T0C IGZO approach eliminates the capacitor, reduces leakage current, and enables better scaling. This innovation opens the door to high-density 3D DRAM stacking and embedded DRAM solutions, potentially disrupting the conventional DRAM roadmap by overcoming the physical limitations of silicon-based transistors and capacitors at advanced nodes.
Key quotes
· 3 pulledThe bit cell of dynamic random-access memory (DRAM), the main memory within traditional compute architectures, is conceptually very simple.
While the capacitor's role is to store a charge, the transistor is used to access the capacitor, either to read how much charge is stored or to store a new charge.
Over the years, bit cell density scaling allowed the industry to introduce subsequent generations of DRAM technology and cope with the growing demand for DRAM.
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