Developing a Low Latency 10G Ethernet Core for FPGA - Introduction

Summary

This is the introductory post in a series about developing a low latency 10G Ethernet core for FPGA as a personal project. The author aims to develop expertise in low latency FPGA design and high-speed Ethernet while experimenting with tools and techniques for potential full-time use. The series will cover design overview, verification, low latency techniques, performance measurement, and potential improvements.